This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In the electronics manufacturing industry, electronic design automation (EDA) generally refers to software tools for designing electronic systems, such as printed circuit boards (PCBs) and integrated circuits (ICs). These software tools are used by designers to design and analyze entire semiconductor chips. In semiconductor design, standard cell methodology provides for a system of methods, principles, and rules for designing digital-logic features and behaviors of integrated circuits. This standard cell methodology allows for design abstraction, where one designer may focus on high-level logical function of a digital design, while another designer may focus on physical implementation of the digital design. Along with advances in semiconductor manufacturing, this standard cell methodology assists designers with designing integrated circuits from single-function IC devices to complex system-on-a-chip (SoC) devices.
FIGS. 1A-1B illustrate diagrams of conventional placement flows as known in the art. In reference to physical design, FIG. 1A illustrates a diagram of a conventional post-synthesis process flow 100A as known in the art, wherein a floorplan 110 of a design may be provided after synthesis 112 of the design. Further, FIG. 1B illustrates another diagram of a conventional pre-synthesis process flow 100B as known in the art, wherein the floorplan 110 of a design may be provided prior to synthesis 112 of the design.
Generally, a typical process flow provides for various operations related to an integrated circuit design, including a floorplan 110, synthesis 112, placement 114, clock tree synthesis 116 and routing 118. The floorplan 110 refers to some gross floor planning choices of the design, such as location of memories, ports, etc. In some cases, synthesis 112 may refer to logic synthesis, which is a process by which an abstract form of desired circuit behavior at register transfer level (RTL) is used to implement a design in terms of logic gates. In other cases, synthesis 112 may refer to high-level synthesis, which is an automated design process that interprets an algorithmic description of a desired behavior and generates digital hardware to implement that behavior. Further, placement 114 refers to assigning locations for various circuit components within a chip area. Clock tree synthesis (CTS) 116 refers to a process of determining various timing patterns of the physical design, including timing skew and delay. Routing 118 refers to a process of allocating routing resources that are used for connections, assigning routes to specific metal layers, and routing tracks within the routing resources.